The data processing speed of digital systems is rapidly increasing. In order to process data at high speed, digital systems require high-speed clock signals. A phase locked loop (PLL) generates and provides high-speed clock signals for digital systems.
The clock signals generated by a PLL have a limited frequency. To overcome this limit, the number of delay cells included in a voltage controlled oscillator (VCO) of the PLL may be increased. However, when the number of delay cells is increased, harmonic lock may occur in the PLL, which can prevent the PLL from functioning properly.